Retro CPC Dongle – Part 41

Build v2.3

So the next build of the CPC2 is done. I recorded the process with a time-lapse camera because it’s hard to make a 7 hour build entertaining. Each second of video is 30 seconds of assembly time, so this 7-hour build ended up at 7m19s of timelapse, after cutting out the cursing and head-scratching. See if you can spot my hands start to shake at the 2-hour mark of trying to precisely place the sub-millimetre components and enjoy.

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Retro CPC Dongle – Part 38

This post talks about HyperRAM, what it is, how to interface to it and how to improve the performance of high-speed parallel interfaces.

HyperRAM is described well by Cypress. It is essentially a double data rate RAM with a compact 12-line interface that masks the underlying technology of a DDR SDRAM.  It can provide 333MB/s of data transfer in short bursts. Data is transferred on both edges of the clock, and the narrow bus makes it ideal for microprocessors or pin-constrained FPGAs. Continue reading

Retro CPC Dongle – Part 37

Tented Vias – who’d have thought they play such an essential role? If you have no idea what tented vias are, then you’re not alone and I’m here to enlighten you.

Sadly, this is not a post documenting success, but another important lessons learned. I mentioned in a previous post that I had tired of my custom hardware failing every time I try to solder the next component to the mainboard, so I opted to work on a development board until most of the RTL was proven, and only then move back to custom hardware. I tried the Cyclone V GX Starter kit, but this was lacking a few features like the USB controller I wanted, and was simply too big. I rapidly switched to the fantastic Terasic DE10-Nano SOC. It had a serial interface, the same ADV7513 video chip as my custom board, SDCard and the same USB PHY. All I needed to add was some memory. The DE10-Nano has two expansion ports, so it’s easy to add a daughter board that provides this memory capability:

DE10 with memory daughter board

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Retro CPC Dongle – Part 36

Another update and another dead end. In an attempt to add the much-needed storage mentioned in my last post, I managed to damage the board so that the JTAG connection stopped working. I added the EPCQ configuration flash chip to the board, only to find that I’d wired the data in and data out back to front and the flash can’t be read from the FPGA. I looked at direct access through the ASMI connection, but I couldn’t get this working. I guess it doesn’t expect the chip to be wired in ‘backwards’! In a futile recovery attempt, I tried to solder in the spare 16G eMMC card, but managed to short out the power pins again. Upon desoldering the eMMC, I must have damaged something because the JTAG connection stopped working. The chip could still be programmed through the supervisor connection on the fast-passive-parallel port, so it was not extensively damaged, but the JTAG connection was pretty essential to efficient RTL development. For now the board is relegated to the ‘post-project-review’ bin. Developing the hardware, RTL and software all in parallel creates too much inefficiency. So I decided to use this board to finish the development, the Terasic Cyclone V GX Starter:

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Making Double Side Boards in a Reflow Oven

I was planning to write up my next big gamble with the CPC2 build; double sided reflow boards. However, someone has done it for me!

With the addition of new components to my CPC2 design it’s starting to look very cramped if I want to keep the small form factor (the dongle part of my CPC2 dongle).

This is usually solved by putting some of the more flexible components, such as passive capacitors and resistors on the bottom of the board. I’d normally do this manually with a hot air pencil. But with the very large number of bypass capacitors that I’ve added to my latest design, hand assembly is not my preferred option, although still possible.

Instead I’m going to try to follow the lead of some of the PCB forums contributors, and bake both sides of the board.

The results seems mixed when both sides are baked using normal leaded solder paste. Usually it works, but sometimes not. However, it seems universally accepted that using lead-free solder on the bottom of the board and leaded solder on the top seems to be successful.

The higher melting point of the lead-free solder will ensure the components on the bottom of the board won’t drop off during the bake of the top side.

Additionally the bottom side of the board is a few degrees cooler than the top side as it’s facing away from the infra-red elements in the oven.

There’s a couple of things I need to do to ensure that this method is viable:

  • Place only high-temperature components on the bottom of the board, so no clocks or precision resisistors
  • Place only low-mass devices on the bottom. The solder has a good surface tension when reflowed, but adding a heavy, 20mm high-bright LED might overcome the surface tension.
  • No precision placed components. While I don’t expect the components will drop off, there will be some semi-liquid solder on the bottom side at the peak reflow temperature, and it’s quite possible they will jiggle during the second bake. An eMMC chip has 0.5mm pitch balls, so there’s no room for any jiggling.

So, that’s my plan. I’ve finished the update of the CPC2 schematic, and I’m laying out the board now. I expect I’ll be done in a few days, then a week of testing and I’ll send the gerbers to my favourite fab OSH Park.

Yes, it’s another shameless plug for a company that enables my hobby! Please support them by sending them your boards for fabrication so that I can keep sending them mine! You’ll also note in the linked Instructibles above, they also use both OSH Park and OSH Stencils. Coincidence….?

Stay tuned for the results in a few weeks.

Working with Surface Mount Components and BGAs

Surface mount PCBs (Part 2 –  BGAs)

In my first post I described the process of reliably soldering surface mount components to create sophisticated and high density PCBs.   Many of the really exciting components are only available in a Ball Grid Array (BGA) package.  Think of ARM processors, high density memory, and Field Programmable Gate Arrays (FPGA).  These complex devices can have too many connections to the silicon to use a traditional Small Outline Package (SOP) or Quad Flat Pack (QFP).   On high pin count QFPs the pins are so narrowly spaced that solder bridges are common and pins are far to easy to bend and damage. Ironically BGAs are easier to work with in this regard as they are intrinsically far more resistant to damage prior to mounting.

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Working with Surface Mount Components and BGAs

Surface mount PCBs (Part 1)

If you look at a circuit board today, you’ll see a beautiful array of surface mount chips and components, including very fine 0.5mm or even 0.4mm leaded devices and BGAs.  Some of these ‘exotic’ devices can contain really advanced technology such as high speed ARM microprocessors, flash and high capacity memory, and FPGAs.  If you’re like me, you’ve looked at these boards and wished that you could produce circuit boards of such fine detail at home, and build projects with these exciting technologies.  Well, I’m here to tell you that it’s not as difficult as it looks.

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