I’ll start with a confession. While I’ve had some success with FPGAs, I managed this despite not understanding some of the basics, such as system design constraints, particularly in Quartus. This post covers both my research into system design/timing constraints and the result of the byte cache that sits on top of the SDRAM controller. I’ll break with my tradition and save the screen grab for the end.
Cache (Screen) Grab (Click for large)
This screen grab shows one of the key process steps in the caching controller, the cache line replacement. The red bracket indicates the cache i/o ports and some key internal state variables, and the blue bracket indicates the data cache i/o ports on the dual-port ram. Continue reading
How time flies – it’s been a month since I posted. I’ve been waiting for the PCBs ordered from OSH Park to arrive. They were tracked all the way from the US to my local post office, and somehow Australia Post managed to lose them 😦 The helpful people at OSH Park didn’t hesitate, they put through another copy of my board on the next production run at no cost to me. They’re on their way already – thank you, OSH Park! I can’t rate these guys highly enough!
So, let’s start with the obligatory graphic:
After a two month absence, I can reveal that the CPC2 has another component almost ready for prime time. The past few weeks have been spent writing the Verilog RTL code for the uPD765 floppy disk controller, from scratch. It was one of the more interesting and sophisticated functions that I’ve written. Take a look at this “proof of life”:
Well, my capture card arrived! No more shaky video. Here’s the current state of my CPC2.0. I’ve faked a keyboard to type in |m,1 to start the Arnor disassembler.
Recognise this screen? It’s a little distorted, but it’s getting there!
I managed to create the ‘hardware shim’ that would allow the Verilog RTL to run on my new DE10-Nano. This is the first output from the RTL image. A few problems, but promising!
I unboxed the Terasic DE10-Nano! What a great bit of kit for a bargain price of $130! Nice going Terasic – you build some amazing stuff. I couldn’t buy the components for that price! Here it is, plugged into my development box.
The cables are (anti-clockwise from 11), 5V/2A power from the power brick, USB Blaster connection, Ethernet plugged direct into my dev box (no crossover or switch), FTDI UART console.
There are two images available from the Terasic site, an Ubuntu image with full LXDE GUI, or a console image. I started with the Ubuntu image, just because it had a great ControlPanel App to show linkage to the DE10.
The screen shot below says it all. Yay! Video output from the CPC2.0!
I promised myself that I wouldn’t post those shaky photos/videos that people seem to post of their game/emulator/screen. Unfortunately, at this time a photo of the screen is the best I can do. Longer term, I’ll get a HDMI capture card from eBay and capture the screens properly, but for now this will have to do as proof of success! Colour bars. Continue reading
Developing a complex embedded system like the CPC2.0 from scratch is a series of massive achievements in miniature, like a nano-scale thunderstorm. Huge steps forward are represented by a signal line going high, or a chip outputting a short sequence of bits, proving the framework of everything built to date. This project is just like that, so it’s tough to explain to people that those few numbers on the screen represent thousands of hours of coding in C, RTL and hardware design to get a coded sequence out of the HDMI chip. There can be a lot of effort behind a blinky LED.
So, to make it a more interesting post, I thought I’d start with this: