Retro CPC Dongle – Part 30

 

“Cache Grab”

Yes, pun intended, this post is about the caching SDRAM controller that I’ve written for the new CPC2.2 board. Here’s the cache (screen) grab:

Cache (Screen) Grab (Click for large)

This screen grab shows one of the key process steps in the caching controller, the cache line replacement. The red bracket indicates the cache i/o ports and some key internal state variables, and the blue bracket indicates the data cache i/o ports on the dual-port ram. Continue reading

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Retro CPC Dongle – Part 29

How time flies – it’s been a month since I posted. I’ve been waiting for the PCBs ordered from OSH Park to arrive. They were tracked all the way from the US to my local post office, and somehow Australia Post managed to lose them 😦 The helpful people at OSH Park didn’t hesitate, they put through another copy of my board on the next production run at no cost to me. They’re on their way already – thank you, OSH Park! I can’t rate these guys highly enough!

So, let’s start with the obligatory graphic:

Simulating the SDRAM controller, connected to a Z80! (Click for large)

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Retro CPC Dongle – Part 23

I unboxed the Terasic DE10-Nano! What a great bit of kit for a bargain price of $130! Nice going Terasic – you build some amazing stuff. I couldn’t buy the components for that price! Here it is, plugged into my development box.

DE10-Nano (Click for Large)

The cables are (anti-clockwise from 11), 5V/2A power from the power brick, USB Blaster connection, Ethernet plugged direct into my dev box (no crossover or switch), FTDI UART console.

There are two images available from the Terasic site, an Ubuntu image with full LXDE GUI, or a console image. I started with the Ubuntu image, just because it had a great ControlPanel App to show linkage to the DE10.

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