The CPC disk operations are working! The video below shows the CPC loading a disk image from the eMMC, saving new files and unloading the disk image back to the eMMC. The image on the right is the UART console, which is also used to issue the mount and unmount commands (via ‘m’ and ‘u’ commands).
Since my last post, I’ve been beavering away on the SPI interface between the Atmel supervisor chip and the FPGA. The SPI interface is almost ready to share, but not quite. In the meantime, I’ll share the little side project I’ve been working on, replacing the NAND raw flash with an eMMC chip on the CPC2.0 board.
I wrote about raw flash and the challenges of writing a flash translation later in part 16 of this series. After some research, I concluded that the eMMC interface looked exactly like the much more common SDCard interface, albeit that the interface can be run with an 8-bit width. SDCards are limited to 4 bits by the physical pin count. Taking a gamble I created a board to test this new eMMC chip. I created a fake SDCard!
This fake card allowed me to check very quickly if my assumptions were correct both at a hardware and a firmware level. I wanted to be sure that it was possible to interface the eMMC via 4 bits, rather than the full 8 bits and be sure the firmware instructions were the same between these two technologies.
The Atmel SAM4S chip has a hardware interface for SDCards. If the eMMC worked with the SDCard interface, I just needed to hook up the eMMC to the Atmel SAM4S chip using the built-in HSMCI interface. I could then use the libraries provided in the Atmel Software Framework to interface to the card. No effort required and definitely no flash translation layer required!
It’s been a while since my last post, so I thought it about time I provided an update. I’ve been working on the supervisory software inside the SAM4 microcontroller.
Here are the planned features for this chip:
- Flash management including flash translation layer
- MRAM management
- Provide an interface to the FPGA to access these two memories
- Provide a debug console for both the monitor program and the FPGA
- Provide an upload facility to both the FPGA and to memory
To date, I’ve:
- Written the MRAM interface, using the Atmel ASF libraries to handle the SPI
- Connected and passed traffic between the FPGA and the SAM4 supervisor using the 40MHz SPI interface
- Started the user interface for the monitor program. At the moment, all it shows is one active item to upload the bitstream to the FPGA and several templated inactive items.
- Connected and can read/write the RAW flash layer
Where I’ve gotten bogged down is in the flash translation layer (FTL). Continue reading