The Terasic DE0-Nano is an excellent device, but it lacks an easily accessible UART to get information in and out of your design.
Fortunately, Altera’s Virtual JTAG functionality allows easy access to logic inside of your design. Chris Zeh wrote an excellent article on this Virtual JTAG functionality and how to easily send data in and out of the chip. You can read his blog entry here.
This Virtual UART project is an extension of Chris’s work. It provides a Verilog template to expose a parallel FIFO interface into and out of your design, matched to a TCL script on the PC side. It allows a simple way to talk to your logic design through a character interface – ideal for a terminal interface to your latest NIOS or OpenRISC SoC.
The example TCL script sets up a network connection on your PC, listening on port 2323. Using Telnet to connect to this port will parse the Virtual JTag instructions to get data in and out of the Virtual UART buffers.
The quickest way to get started is to run the pre-compiled images provided here. When you’re ready to incorporate this into your own design, all source is available on Github.
Even with no additional hardware, adding a Virtual UART to your design makes the DE0 Nano even more accessible. If you find this useful, let me know in the comments!