Retro CPC Dongle – Part 13

SUCCESS!

Yes, you read that correctly. I managed to get the board working from my last post. Lucky post 13! I removed the SDRAM chip and the short between GND and the 3.3v line disappeared. Perplexed, I re-checked the data sheet and yes, I’d made a mistake. There are three VCC and three VSS pins. I’d transposed the last two of these. Ah well. This board was never going be the final build anyway, so I just removed the SDRAM chip with my hot air hand tools.

The regulators and inductors were still running hot, so I suspected there was a further issue, but the LED was alight now, which was a good sign. The voltages out of the regulators were a bit low, so I checked some key components, such as the clocks and lo-and-behold, I’d placed the 50MHz oscillator at 90 degrees out. These chips are 2mmx3mm, so excuse this minor fault. I removed the oscillator and the line voltages returned to tolerance and the heat in the regs and inductors went away. Woohoo!

I soldered on the JTAG port for my Atmel-ICE programmer and programmed an initial hello world program. I upped the PLL so that the ARM core ran at 120MHz and it was quite stable. If you switch from low speed to maximum clock it sucks a huge gulp of power from the supply lines, so if the regs, inductors and noise suppression capacitors are not sufficient the core self-resets. I didn’t see any behaviour like that, so I’m confident the Atmel SAM core is good.

I also found a few other stupid mistakes, like I’d provided a jumper to erase the ARM microcontroller, but jumpered it to ground and it needs +3.3v to erase. I also managed to set the security bit while fiddling with the programmer, so I was locked out of the chip. Luckily, the Atmel-ICE cable has two connectors, both a 0.05″ and a 0.1″ pitch connector. So I took 3.3v from this ribbon connector and zapped the erase pin during power up and wiped the security bit, allowing me back into the chip programming mode.

I wrote a quick program to toggle the FPGA configuration lines and managed to get an acknowledgement level-shift on the status line, so all good so far! I tried to get a fault condition, by sending zeros and all-ones to the FPGA, but couldn’t elicit a fault response, so I suspect it’s waiting for specific value before it starts it’s configuration process.

As I write this, I’m installing Altera Quartus on my new HP all-in-one, so that I can create a bitstream simply to turn off the LED (it defaults to on) and see the CONF_DONE line go high. That’s probably some way away, but I thought it worthwhile to report this success after another apparent failure.

I’ll be able to test the other components on this build, so it’s not a waste and I’ll perfect the supervisor programming software and test the remaining components before the next build.

Stay tuned for my next post!

Retro CPC Dongle – Part 12

Welcome back to the next part of this retro adventure. Last time, I told you the new boards are back from the fabrication house. These are the same logical design (called schematic) as the previous boards, but use a different and simplified layout and I’ve removed some components to make the assembly easier. I also changed my assembly approach.

I’m pleased to say I had a 50% success rate, which is 49% better than last time! The board assembled beautifully.

Unfortunately, I still have some problems but let’s go through the new assembly process before we go further. As I mentioned last time, I intended to assemble the board using a dry layout process first. This means I can take all the time I need to get the components out of their packaging and lay them out on the board and not worry about whether the solder paste is going off. Continue reading

Retro CPC Dongle – Part 10

Following my last post, I’ve updated the board layout to correct the mistakes of my previous work. Let’s start with the board renders from OSH Park.

CPC2.1 Board Top – OSH Park Render
CPC2.1 Board Bottom – OSH Park Render

While the layout is quite different from the previous version, the schematic is quite similar. I’ll talk through the changes in this version and the method that I used to build this layout. Continue reading

Retro CPC Dongle – Part 9

OK, so I had a setback. Not a major one, but enough to make me want to go back and redo the design and incorporate all of the learning to date on this project. The key mantra for me is “simplify, simplify, simplify”. If I can do more of the complexity in software rather than hardware without sacrificing the goals of the project, then I’ll do that.

Below is an updated block diagram. Compare this to the original and you’ll see that I’ve simplified the memory interface to connect through an Atmel SAM4S processor. This will handle configuration of the FPGA as well as handling the system storage and pass the data through the support CPU. The system interface (system I/F) will be a fast interface to the internal structures of the FPGA.

Updated Block Diagram

The flash memory is required to be connected to the SAM4S because this will also handle the FPGA configuration through the passive parallel port and needs the storage of the flash device to hold the FPGA images. The MRAM is also connected to the SAM4S as this will be used to manage regular configuration changes and assist with the flash translation layer (FTL).

Moving the storage devices off the FPGA will reduce the number of pins required for connection to the FPGA, making the wiring of this device simpler. I’ve added an ESP32 module from Espressif to handle Bluetooth and Wifi. This won’t be available on the first incarnation of the board, but will be added later as the ESP32 becomes available for sale.

So, same functionality, simplified connections, fewer components.

Watch this space.

 

Retro CPC Dongle – Part 7

In my last post, I reviewed the board that came back from OSH Park. Within a week I’d also received my stencil from OSH Stencils. Seriously impressive guys! Last time I ordered it took a month to arrive in Australia, this was a week and a half. Not only that, I opted for both the plastic and the stainless steel stencil to compare the fine detail on each. The plastic stencils are fine for larger print, but on my last project, I struggled to get the solder paste to print through the fine 0.4mm holes for the BGA. I may be able to apply more pressure to the steel stencil to get the paste through. Here’s the nice little package from OSH Stencils.

Note the nice little touch with the solder paste spreader and the OSH Stencils sticker for your laptop/bike/pencil case.
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Retro CPC Dongle – Part 6

This picture says it all, my boards are back from the fab lab!

 

Finished Board (Click for hi-res)

 

Following on from my last postOSH Park came up with the goods again! Within three weeks of submitting the design, the finished boards were in my eager hands. A quick electrical test and brief inspection under a microscope convinces me these are manufactured to spec.

Continue reading

Retro CPC Dongle – Part 5

Exciting news! The CPC2 PCB has gone to the fab lab, OSH Park and is in production as I write this.  I probably should have been reporting progress over the past few months on the schematic and PCB layout, but I’ve opted to use my precious spare time to lay out the PCB so that I know it all fits together before posting. Without further delay, here’s the finished board layout, rendered by the OSH Park service:

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Retro CPC Dongle – Part 4

In my last post I evaluated the technical feasibility of memory timing in the expected architecture of the CPC dongle. I’m now confident that the key components that I’ve chosen will work for this project.  I now have to start getting the design into a design tool. This time I will take you through how to get the schematic and pin/pad layouts into your Electronic Design Automation (EDA) tool, such as DesignSpark from RS Components  so that you can produce something like this:

Image courtesy of Designspark

This step  is one of the critical steps in any electronics project, piecing together the components to achieve the outputs that you’re looking for. Even if you don’t intend to build the project yourself, when done properly, you can send these designs to fabrication and assembly labs who can put this device together for you.

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Retro CPC Dongle – Part 3

In the last post, I laid out the hardware and architecture planned for this USB-sized 8-bit home-computer. Since then, I’ve been developing the various components in Verilog and testing some of the unknowns. Specifically, I’ve been trying to work out if the memory chip has the required bandwidth for my device.

To do this, I need to study the datasheet for the SDRAM device and understand the best and worst case operating parameters.  One timing diagram for a burst read operation is shown below:

We can see from this that there is a delay between the read operation and the availability of the data.  In the example above, it shows that for every 6 clocks, we get data available during 4 of those T-Cycles.  Combining this information with the expected operating profile is critical to determining if we can service the expected memory requests.

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