After a two month absence, I can reveal that the CPC2 has another component almost ready for prime time. The past few weeks have been spent writing the Verilog RTL code for the uPD765 floppy disk controller, from scratch. It was one of the more interesting and sophisticated functions that I’ve written. Take a look at this “proof of life”:
Mad props to antepher and his awesome techtutorialsx blog. Just when I’d given up hope that the ESP32 would resolve my Bluetooth woes, he points out that BTStack is a pretty capable stack for embedded and has a port for the ESP32 already! I’m eternally grateful…thank you! More to come, but I may be able to get the ESP32+BTStack to connect to my Bluetooth HID devices for CPC2…
The objective of this ESP32 tutorial is to explain how to get started with the Bluetooth functionalities that are supported by the ESP32 hardware. The Bluetooth tests of this tutorial were performed using a DFRobot’s ESP-WROOM-32 module, integrated in a ESP32 FireBeetle board.
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Lab Power, Timing issues, Dodgy eBay Vendors, ESP32 and Sound!
This is a multipart post to get some of the project activities over the past couple of weeks documented. Let’s start with “Lab Power!”
Following the last post, I connected the USB packet information to the faked keyboard in the FPGA and managed to get this.
There’s a timing issue that I suspect is interrupt related. The key repeat is extremely slow, and this is mainly driven from the 50Hz interrupt line. I faked this signal, so there’s obviously some work to do there! Stay tuned!
What’s wrong with this picture? (Impedance matching and other things)
It’s about time we talked about high speed signals, impedance matching and signal reflections. Take a look at this picture:
There is something clearly wrong with the image above, the pixels are all there and the colours are almost right, but what you’re seeing above isn’t what was sent from the FPGA. What I think I’m seeing here is signal trace length skew and signal reflections.
Well, my capture card arrived! No more shaky video. Here’s the current state of my CPC2.0. I’ve faked a keyboard to type in |m,1 to start the Arnor disassembler.
Recognise this screen? It’s a little distorted, but it’s getting there!
I managed to create the ‘hardware shim’ that would allow the Verilog RTL to run on my new DE10-Nano. This is the first output from the RTL image. A few problems, but promising!