I was planning to write up my next big gamble with the CPC2 build; double sided reflow boards. However, someone has done it for me!
With the addition of new components to my CPC2 design it’s starting to look very cramped if I want to keep the small form factor (the dongle part of my CPC2 dongle).
This is usually solved by putting some of the more flexible components, such as passive capacitors and resistors on the bottom of the board. I’d normally do this manually with a hot air pencil. But with the very large number of bypass capacitors that I’ve added to my latest design, hand assembly is not my preferred option, although still possible.
Instead I’m going to try to follow the lead of some of the PCB forums contributors, and bake both sides of the board.
The results seems mixed when both sides are baked using normal leaded solder paste. Usually it works, but sometimes not. However, it seems universally accepted that using lead-free solder on the bottom of the board and leaded solder on the top seems to be successful.
The higher melting point of the lead-free solder will ensure the components on the bottom of the board won’t drop off during the bake of the top side.
Additionally the bottom side of the board is a few degrees cooler than the top side as it’s facing away from the infra-red elements in the oven.
There’s a couple of things I need to do to ensure that this method is viable:
- Place only high-temperature components on the bottom of the board, so no clocks or precision resisistors
- Place only low-mass devices on the bottom. The solder has a good surface tension when reflowed, but adding a heavy, 20mm high-bright LED might overcome the surface tension.
- No precision placed components. While I don’t expect the components will drop off, there will be some semi-liquid solder on the bottom side at the peak reflow temperature, and it’s quite possible they will jiggle during the second bake. An eMMC chip has 0.5mm pitch balls, so there’s no room for any jiggling.
So, that’s my plan. I’ve finished the update of the CPC2 schematic, and I’m laying out the board now. I expect I’ll be done in a few days, then a week of testing and I’ll send the gerbers to my favourite fab OSH Park.
Yes, it’s another shameless plug for a company that enables my hobby! Please support them by sending them your boards for fabrication so that I can keep sending them mine! You’ll also note in the linked Instructibles above, they also use both OSH Park and OSH Stencils. Coincidence….?
Stay tuned for the results in a few weeks.
After a two month absence, I can reveal that the CPC2 has another component almost ready for prime time. The past few weeks have been spent writing the Verilog RTL code for the uPD765 floppy disk controller, from scratch. It was one of the more interesting and sophisticated functions that I’ve written. Take a look at this “proof of life”:
Mad props to antepher and his awesome techtutorialsx blog. Just when I’d given up hope that the ESP32 would resolve my Bluetooth woes, he points out that BTStack is a pretty capable stack for embedded and has a port for the ESP32 already! I’m eternally grateful…thank you! More to come, but I may be able to get the ESP32+BTStack to connect to my Bluetooth HID devices for CPC2…
The objective of this ESP32 tutorial is to explain how to get started with the Bluetooth functionalities that are supported by the ESP32 hardware. The Bluetooth tests of this tutorial were performed using a DFRobot’s ESP-WROOM-32 module, integrated in a ESP32 FireBeetle board.
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Lab Power, Timing issues, Dodgy eBay Vendors, ESP32 and Sound!
This is a multipart post to get some of the project activities over the past couple of weeks documented. Let’s start with “Lab Power!”
Following the last post, I connected the USB packet information to the faked keyboard in the FPGA and managed to get this.
There’s a timing issue that I suspect is interrupt related. The key repeat is extremely slow, and this is mainly driven from the 50Hz interrupt line. I faked this signal, so there’s obviously some work to do there! Stay tuned!
What’s wrong with this picture? (Impedance matching and other things)
It’s about time we talked about high speed signals, impedance matching and signal reflections. Take a look at this picture:
There is something clearly wrong with the image above, the pixels are all there and the colours are almost right, but what you’re seeing above isn’t what was sent from the FPGA. What I think I’m seeing here is signal trace length skew and signal reflections.