Retro CPC Dongle – Part 34

Following a summary of the timing closure challenges in my last post, here’s a few more lessons learned from the process of trying to get my SDRAM and DMA controller to run at their fastest possible speed.

A lot of my timing closure process involved changing the RTL code and checking the effect on the timing. It’s a slow and laborious process, so here’s a list of my findings so you can save the hours of compilation time that it took me to test these.

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Retro CPC Dongle – Part 33

Hello CPC fans! Has it really been 4 months since my last post? How time flies. Thanks to codepainters for the prompt to get going on my next post, and for reminding me that there are readers following the progress of this project.

I spent the first 3 months of this year refining the caching SDRAM controller and chasing timing closure issues. The SDRAM controller and it’s byte cache worked absolutely fine in simulation but failed to work reliably when I put the design in silicon at high speed. The sort of random and unpredictable behaviour I saw is usually indicative of timing issues, (especially when it worked at lower speeds), so I turned my attention to the timing reports from Quartus. This was new ground for me. I knew that IO timing was something that I should pay attention to, but until today my designs generally ran at sub 50MHz speeds where there’s enough timing slack to not notice the issues. However, on every design I’ve ever produced, at least one or two of the Timequest reports were in red, meaning that there were timing violations and hidden problems waiting to rear up when I least wanted them to. Continue reading

Retro CPC Dongle – Part 32

Well, as promised in my last CPC2 post, I finished the next build of the CPC2 board and learned a lot of things during the process. Somethings worked, some things didn’t, but every build is giving me a wealth of knowledge of product design, fault diagnosis and rectification work. Yes, de-solder braid really was my best friend in this build!

Finally, a working board (click here for large)
Bottom side of board (click here for large)

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Retro CPC Dongle – Part 31

I’ll start with a confession. While I’ve had some success with FPGAs, I managed this despite not understanding some of the basics, such as system design constraints, particularly in Quartus. This post covers both my research into system design/timing constraints and the result of the byte cache that sits on top of the SDRAM controller. I’ll break with my tradition and save the screen grab for the end.

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Retro CPC Dongle – Part 30

 

“Cache Grab”

Yes, pun intended, this post is about the caching SDRAM controller that I’ve written for the new CPC2.2 board. Here’s the cache (screen) grab:

Cache (Screen) Grab (Click for large)

This screen grab shows one of the key process steps in the caching controller, the cache line replacement. The red bracket indicates the cache i/o ports and some key internal state variables, and the blue bracket indicates the data cache i/o ports on the dual-port ram. Continue reading

Retro CPC Dongle – Part 29

How time flies – it’s been a month since I posted. I’ve been waiting for the PCBs ordered from OSH Park to arrive. They were tracked all the way from the US to my local post office, and somehow Australia Post managed to lose them 😦 The helpful people at OSH Park didn’t hesitate, they put through another copy of my board on the next production run at no cost to me. They’re on their way already – thank you, OSH Park! I can’t rate these guys highly enough!

So, let’s start with the obligatory graphic:

Simulating the SDRAM controller, connected to a Z80! (Click for large)

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