So the next build of the CPC2 is done. I recorded the process with a time-lapse camera because it’s hard to make a 7 hour build entertaining. Each second of video is 30 seconds of assembly time, so this 7-hour build ended up at 7m19s of timelapse, after cutting out the cursing and head-scratching. See if you can spot my hands start to shake at the 2-hour mark of trying to precisely place the sub-millimetre components and enjoy.
It took a while to get things together for this build as I had to source parts of the build from a multitude of sources. I talked in my last post about the obsolescence of some of the key components. The boards I ordered from OSH Park arrived with a manufacturing defect where some of the ENIG was missing, however, one quick email and a few close-up photos of the missing ENIG on copper and the team there ordered replacements with no fuss at all. Great job OSH Park. After about 6 weeks, all the parts had arrived and were ready for assembly. I took a day of work for the build because I wanted to finish this in a single session, rather than run it over several days as I had before.
The build started at 9 am sharp. I approached the assembly with much less trepidation and nervousness this time. I have a good process and it’s not let me down. The only time that it failed was with poor stencilling or a poor pad layout. I was hoping that I’d nailed it this time.
The board is designed with most of the passives on the bottom side of the board, so this is where I started. These were mounted with lead-free solder, so they do not reflow or move when I reflow the top components. On the top was all of the large, complex and expensive components, like the FPGA. So if I stuffed up the bottom side of the board, I’d wasted at most $20 of passives and a PCB and I can restart with another board.
The process I have created and carefully observe is as follows:
- Inspect the boards and select the best candidate. I’m looking for solder mask registration, and silkscreen quality, as well as the smallest break-away tabs for easy deburring. Clean the selected board with alcohol.
- Check the paste stencil alignment with the board. If all is well, put aside the selected board, it will be used later.
- Mark off all of the bottom side components from the bill of materials, by cross-referencing them with the PCB layout.
- Once all of the bottom side components have been identified, I use the list sorted by component type and value. For example, all capacitors of 100nF then all 1uF caps, then all 10uF caps, then all resistors and so on. These are scattered across the board and can be tricky to place without disturbing neighbouring components, but exact placement isn’t a problem in a dry placement.
- Every component is checked for an approximate location using the PCB tool, so that’s it easier to find and that is why you’ll see me checking the PCB layout tool during placement. Each item is ticked off the BOM as it is placed.
- After placing all of the resistors, capacitors, inductors, and voltage regulators required on the bottom side, I move onto mounting the paste stencil over the selected board (1:50 in the video). Pasting the bottom side of the board is easy as the stand-offs raise the stencil to a height that matches the PCB thickness. (Thanks to OSH Stencils for making this process easy!)
- A quick splash of solder paste on the board and a firm even spread to get this onto the pads and the pasting is done.
- The next step is to move every component from the ‘dry’ board to the ‘wet’ board with the solder paste. This process is very quick and avoids the solder paste spreading during placement. As I am right-handed, I work from left to right and top to bottom. This two-step placement avoids the time-consuming location and extraction of the components from their carrier while the paste ‘goes off’. It is also less likely to disturb nearby components as my dominant hand is always to the right of the existing place components. The migration of components took less than 12 minutes (23 seconds of video), despite it being a much more precise placement compared with over an hour for the dry placement.
- Next, the board is baked on a lead-free profile (2:30). A quick inspection of the board after reflowing confirms that the lead-free solder has reflowed properly.
- The top layer is placed in the same way as the bottom layer, in any order of preference, generally from smallest to largest components onto a dry board.
- After the dry placement is complete, pasting of the final board takes place (4:00). This is trickier because there are components on the bottom side of the board so that it can’t sit flat on the mounting surface. I use a couple of old PCBs to raise the board off the mounting surface and provide a flush surface for stencilling the top layer. A quick visual inspection of the paste placement and it is onto the dry to wet migration process for a second and final time. If you’re wondering about the paper towel in the migration video segment, it is used to remove any solder paste picked up accidentally by the tweezers.
- At 4:35, is a shot of the board immediately after reflow and the sharp-eyed might notice some bridging on the HDMI pins. This was caused by nothing more than excess solder on the pads, due to the oversize stencil mask. The PCB layout tool that I use makes the stencil aperture slightly larger than the pad to ensure sufficient solder gets onto the board. For these component sizes, this oversize is unnecessary and causes solder bridging. I must remember to fix this if there’s another build.
- De-bridging and cleaning involve using de-solder braid to remove excess solder. An optical inspection microscope is essential here as any tiny solder bridges need to be cleaned up to avoid short circuits.
- Initial testing is a pretty crude and consists of nothing more than applying power and seeing if the power indicator lights up, so signifying that the +3.3v line is not shorted to ground (5:38) followed by thermal tests of the regulators (5:58) with a sensitive finger 🙂
- After I have confirmed there’s no short, I add the large connectors for JTAG and proceed with a JTAG data path test. The FPGA is recognized!
- While the video finishes at that point, I continue on and test various parts of the board, and add the ESP-WROOM-32 as well as patch leads for the programming of this module.
- A quick power-up to check the power LED illuminates and I was sure that there were no shorts on the main 3.3v line.
So this build wasn’t perfect. There were several problems:
- The mounting holes for the BOTH of the USB support posts were too small and I couldn’t get the mounting posts through. These had to be clipped off.
- One of the capacitors was laid out in an 0804 footprint rather than a 0603. Fortunately, they’re fairly interchangeable and a 0603 device fit.
- The ESP-WROOM-32 was located on the bottom side of the board and would have benefitted from a top-side placement. I manually reflowed solder paste to mount the ESP-WROOM-32 but the solder paste didn’t reflow properly because I didn’t hold the heat long enough. As a result, the 3.3v line was shorted to ground (why put these pins next to each other anyway?). Reflowing on the reflow oven would have avoided this issue. I had to rework the pad to fix this by simply apply 450C for a few seconds. The solder visibly reflowed and the joint became bright.
- …but the biggest problem was that the footprint for the UART was wrong. I used the footprint for the FT2232H rather than the FT2323R. It was 3mm smaller on each side and simply wouldn’t fit. Unfortunately, this is one of the more critical components for the development board, as it allows me to monitor what’s going on inside the CPC. This was a major problem because it prevented testing any other component as I couldn’t see the results of my test. This chip had to be left off.
Working around the missing UART
So faced with a board that lacked a UART, I started to consider options. The most obvious was that a UART could be provided by the JTAG pins, as I’ve written a module for this before. However, this would be cumbersome and I couldn’t use picocom as the communication tool. It certainly wouldn’t be useful in a production environment.
The next best thing would be to get the Bluetooth UART working and in a weekend, with no prior knowledge or experience, this is exactly what I managed to do. I used the Bluetooth SPP demo that is provided with the ESP32 SDK to forward traffic on UART0 to the Bluetooth connection and forward incoming traffic on the Bluetooth connection to the UART.
I developed the software on the HUZZAH32 Feather. Once it was working, I flashed the program onto the ESP-WROOM-32 board using the JTAG connection through a USB Blaster.
openocd -f interface.cfg -f board/esp-wroom-32.cfg -c "program_esp32 build/bootloader/bootloader.bin 0x1000 verify exit" openocd -f interface.cfg -f board/esp-wroom-32.cfg -c "program_esp32 build/partitions_singleapp.bin 0x8000 verify exit" openocd -f interface.cfg -f board/esp-wroom-32.cfg -c "program_esp32 build/application.bin 0x10000 verify exit"
interface usb_blaster reset_config none
If you’re not repeatedly changing and uploading code, then this is a perfectly acceptable way to flash the ESP32 memory. It takes a bit longer, in the order of 3 minutes or so, but only needs a simple JTAG connection rather than the convoluted reset and UART0 used by the HUZZAH32 (and most other ESP-WROOM-32 boards). Also, don’t believe what you read in the forums, the JTAG reset signal is not needed for a programming process. The Altera USB Blaster does not have a JTAG reset and it worked fine to program the WROOM32. Note that I had to compile OPENOCD from source for the ESP32 to be recognized by OPENOCD. The standard SDK build recognizes the USB Blaster interface, but wouldn’t connect to the ESP32 properly. Follow the instructions at the Espressif site to build and set up OPENOCD and your JTAG debugging interface.
I used the same USB Blaster on the JTAG header to program the FPGA with a test program to check the clock in and LED out signals. This worked fine. Unfortunately, attempting to flash this to the configuration flash memory didn’t work and the process failed in Quartus. Interestingly, I noted the same failure in my last build, and I thought I’d fixed this by swapping the DI/DO pins, but something was still wrong. I’ll have to investigate this further at a later time.
So, apart from the flash failure, the initial tests look promising. Most of the reflow work looked great, with the chips centred on their footprints. I added a loopback for the Bluetooth serial port through the FPGA and that worked great, so I’m assuming that the entire data path should be OK.
The next step is to update my custom Quartus project for the new board and pin connections, then recompile and upload via JTAG. If I’m lucky, then most of it will work, if not then it will be a step-by-step systematic test of each subsystem to see if I can figure out what’s wrong. Fingers crossed.
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