Tented Vias – who’d have thought they play such an essential role? If you have no idea what tented vias are, then you’re not alone and I’m here to enlighten you.
Sadly, this is not a post documenting success, but another important lessons learned. I mentioned in a previous post that I had tired of my custom hardware failing every time I try to solder the next component to the mainboard, so I opted to work on a development board until most of the RTL was proven, and only then move back to custom hardware. I tried the Cyclone V GX Starter kit, but this was lacking a few features like the USB controller I wanted, and was simply too big. I rapidly switched to the fantastic Terasic DE10-Nano SOC. It had a serial interface, the same ADV7513 video chip as my custom board, SDCard and the same USB PHY. All I needed to add was some memory. The DE10-Nano has two expansion ports, so it’s easy to add a daughter board that provides this memory capability:
As you can see, the board has footprints for two BGA memory chips. Unfortunately, the footprints are still unoccupied because of a simple mistake when producing the Gerbers for OSH Park.
Take a close look at the boards:
Pay particular note to the via between the pads on the BGA. You’ll note they’re disturbingly close to the pads and have no solder mask protecting them. During the build of these boards the paste application will smear across pads and vias and short the pad to the nearby via. Surface tension usually clears this up under heating, but only if the gap is big enough for the solder to wick to its nearest neighbour without bridging.
Here’s how it looks under a microscope. Note the extremely small spacing between the pad and the via.
That tolerance is pretty much guaranteed to fail in the assembly. Solder mask provides some isolation between the BGA pins and a tented via is the way to provide solder mask over the copper annular ring between pins and keep the via inaccessible to solder paste and therefore prevents bridging.
Here’s a good image of a tented via. Note the green solder mask at the top of the via keeping the solder paste off the copper.
Even if the via hole isn’t completely covered, the copper annular ring should be covered and prevent solder paste from shorting a pin to a nearby via.
In design spark there is a single check box that turns these tented vias off:
The solder mask is an negative layer, that is, any shape on the solder mask layer is a “keep-out” for the solder mask. So if the via IS included on the solder mask layer, then it will not be covered by solder mask when the layer is inverted. Make sense? Here’s a comparison of via’s unselected (left) and selected (right):
As you can see above, unchecking the vias box on the solder mask layer only shows uncovered traces on the pads, not in between them. Here’s a close up of the Gerbers of all layers:
I do not want gaps in the solder mask (left) vs what I actually asked OSH Park to manufacture for me (right).
Luckily the three boards cost me less than $10, so mistakes like these are an easy fix. These two layer boards turned around from the US to Australia in less than 2 weeks, so I’ll be putting in my replacement soon. While I did share the board on OSH Park, I’ll not link the faulty board here, but I’ll link the replacement boards so if you want to build your own, you’ll be able to order direct.
I’ll be writing up the new memory that I’ll be using in a post soon, as well as documenting my new essential timing constraint command that might just solve 90% of my timing challenges!
3 thoughts on “Retro CPC Dongle – Part 37”
What’s the magic timing constraint command you’re referring to? Made me curious 🙂
You’re looking for a spoiler? 🙂 My next post will cover MAX-SKEW as well as hyperram.
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