Retro CPC Dongle – Part 36

Another update and another dead end. In an attempt to add the much-needed storage mentioned in my last post, I managed to damage the board so that the JTAG connection stopped working. I added the EPCQ configuration flash chip to the board, only to find that I’d wired the data in and data out back to front and the flash can’t be read from the FPGA. I looked at direct access through the ASMI connection, but I couldn’t get this working. I guess it doesn’t expect the chip to be wired in ‘backwards’! In a futile recovery attempt, I tried to solder in the spare 16G eMMC card, but managed to short out the power pins again. Upon desoldering the eMMC, I must have damaged something because the JTAG connection stopped working. The chip could still be programmed through the supervisor connection on the fast-passive-parallel port, so it was not extensively damaged, but the JTAG connection was pretty essential to efficient RTL development. For now the board is relegated to the ‘post-project-review’ bin. Developing the hardware, RTL and software all in parallel creates too much inefficiency. So I decided to use this board to finish the development, the Terasic Cyclone V GX Starter:

This pre-built board is proven and has lots of IO and is somewhat close to the final design. I had initially considered developing on this Dev Board, but discarded the option because it didn’t have SDRAM (it has DDR2) and no USB 1.1 host. However, it has lots of nice features like a built in JTAG and USB Blaster (for debugging), lots of LEDs (for debugging) and lots of switches (for debugging) and some features shared with my ultimate custom board like the Cyclone V chip (albeit a GX variant), an ADV7513 video chip, 256MB EPCQ, a micro-SDCard and a USB UART.

It also has some convenience features like SRAM to help bridge the gap in debug or testing situations. For example, I can use this SRAM as a frame buffer for the video until I have perfected the SDRAM process.

What put me off initially was the lack of SDRAM and this was such an essential core component that I didn’t think development on this board would be worthwhile for the conversion effort to the final custom version and possible overall failure of the design strategy. However, it does have a 40-pin expansion port and so I’ve decided to just create a new daughter board for the GX starter that will hold both the SDRAM and the USB host chip. This will add the missing functionality and allow me to finish the RTL and software design on this dev board. This should be much simpler and low-risk.

Once the RTL and software is finalised for this board, it should be an easy transition to the final custom build and the custom build won’t require all of the support connections that I had been using during development, such as the JTAG connections for the FPGA. Any issues at this stage will be hardware issues and I won’t be debugging hardware, RTL and software all at the same time wondering where the problem lies.

I’m expecting that I can push on through the development of the software/firmware/RTL parts of this project without too much further drama before coming back to the final hardware iteration.

So look out for more exciting news soon!

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