Retro CPC Dongle – Part 36

Another update and another dead end. In an attempt to add the much-needed storage mentioned in my last post, I managed to damage the board so that the JTAG connection stopped working. I added the EPCQ configuration flash chip to the board, only to find that I’d wired the data in and data out back to front and the flash can’t be read from the FPGA. I looked at direct access through the ASMI connection, but I couldn’t get this working. I guess it doesn’t expect the chip to be wired in ‘backwards’! In a futile recovery attempt, I tried to solder in the spare 16G eMMC card, but managed to short out the power pins again. Upon desoldering the eMMC, I must have damaged something because the JTAG connection stopped working. The chip could still be programmed through the supervisor connection on the fast-passive-parallel port, so it was not extensively damaged, but the JTAG connection was pretty essential to efficient RTL development. For now the board is relegated to the ‘post-project-review’ bin. Developing the hardware, RTL and software all in parallel creates too much inefficiency. So I decided to use this board to finish the development, the Terasic Cyclone V GX Starter:

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