Time for a quick update. I’ve integrated the SDRAM controller, the byte cache, and created some logic to map some of the SDRAM address space to the CPC ROM enable line. I also created some logic to allow the support CPU to push data into the SDRAM. This means that the support CPU can alter the ROM configuration of the CPC2 based on a user-set configuration.
To test the set-up, I created an example ROM that when booted by the CPC, it copies itself to address 0x4000, then dumps 64 bytes of memory at 0x4000. This will test the SDRAM controller, the cache and the cache replacement algorithm. Here’s the output.
It doesn’t look like much, but if you read my last post in timing issues and my attempt to run the logic at anything like the a reasonable speed, this is a fairly satisfying achievement. The supervisor code has been updated to push ROM images into any one of 32 ROM locations in the SDRAM. The SDRAM map looks like this:
- 0x000000 – 0x07FFFF Extended RAM (576K)
- 0x080000 – 0x100000 ROMs 0-31
The rest of the RAM is either used to store the video image or unused for the CPC.
The other trick I used for performance reasons is to hold the lower ROM and the BASIC ROM in block RAM in the FPGA, so that only ROMs 1-31 and the extended RAM will need to work through the caching controller.
I’m still lacking storage on the CPC2, and once this is available, it will open the door to storing proper ROM images and disk images onboard and allow me to get to work on the next step in the supervisor software. I’m going to try one more time to get the eMMC mounted, as I have a spare from my last order. If this works, it will avoid having to create a daughter board to a micro SD card.
More to come.