Retro CPC Dongle – Part 32

Well, as promised in my last CPC2 post, I finished the next build of the CPC2 board and learned a lot of things during the process. Somethings worked, some things didn’t, but every build is giving me a wealth of knowledge of product design, fault diagnosis and rectification work. Yes, de-solder braid really was my best friend in this build!

Finally, a working board (click here for large)
Bottom side of board (click here for large)

In the images above, you might notice a few components are missing. On the top side of the board, from left to right the following components are missing:

  • ESP-WROOM32 bluetooth & WiFi daughter board
  • 16GB eMMC storage chip
  • 256MB FPGA configuration flash chip
  • Microchip USB3320 USB2 controller
  • USB-A Connection (because the controller was removed)

On the bottom side, the ESP JTAG connector is missing, because the WROOM is not installed. You may also note that I haven’t cleaned off the excess flux yet around the pin headers and Mini USB-B connector. Let’s start by describing the build process.

Assembly – Day 1

Assembly started, as usual, with a lot of nerves. I’d put off this build for weeks because I needed the perfect time to concentrate (not easy with young children in the house!). I finally dedicated time over 3 days to complete the build in stages.

I started by testing my double-sided board theory from a few posts ago, and started with the bottom side of the board. This was less densely populated and only held simple passives, so if it went wrong, then I’d junk it and start again with another of the three boards that I got from OSHPark.

As with previous builds, I used a spare copy of the CPC2 board to dry-mount the components first. This served three purposes:

  1. I wasn’t under time pressure to mount the components before the solder paste went off or spread into a sticky mess across the board.
  2. It allowed me to calm my nerves and practice the precise placement of the components without smearing solder paste over my tools or components.
  3. I can work in component order, that is, placing all 100nF capacitors first, then go onto 10uF inductors, and so on. It saves multiple handing of the component packaging.

Dry placement of the passives on the bottom side of the board took about 90 minutes. Every movement was slow and deliberate and any slip or knock on the workstation could skew the components and I’d have no idea what was what. SMT is notoriously poorly identifiable. Once the entire bottom side was placed, I grabbed a second board and used the paste stencil from OSH Stencils to smear solder paste through the stencil onto the board. After gently lifting the stencil and inspecting the result, it looked really good, with tight placement of the paste.

Next, I would transfer the components from the dry board to the pasted board. This time, I could work from left to right and top to bottom. As I’m right handed, this was most natural and avoided knocking already-placed components. This relocation took about another 30 minutes. I gingerly placed the board in the reflow oven and baked the board.

I was using lead-free solder on bottom side hoping that with a higher melting point, it’s unlikely to become liquid causing the components fall off when I bake the top side. My reflow oven has several profiles and using the lead-free profile is significantly hotter than leaded reflow profiles, as evidenced by the horrendous smell of something burning as it cooked.

However, I inspected the finished board and it looked OK, although I didn’t like the look of the lead-free solder. It had a sort of mottled appearance that made it look poorly finished.

Close up of the large lead-free solder erase pads

Ignore the yellowish goo, this is paste flux residue that would need to be cleaned off later. The mottled effect was evident across the board. However, all of the components self centered correctly under reflow, with no misalignment and no solder bridges. So far, so good! Day 1 was done, 2.5 hours.

Assembly – Day 2

This begins with a re-inspection of the board followed by working out how the heck I would use the paste stencil with a board that is raised up about 2mm from the work surface by the bottom side components. I decided that the width of two PCBs was enough to raise the board off the work area to give a flat stencil area. I prepared the paste stencil first. I mounted two ‘junk’ boards at either end of the CPC2 PCB to raise the board and used the OSH Stencils jig to stabilise the paste area. The OSH Stencils site was down at the time of writing so I couldn’t get an image of their jigs, but I found this via google, so you can see what the jig looks like.

In retrospect, I should have ordered two more jigs and used two to raise the board up and the third to secure the paste area, creating a void underneath the stencil area to give room to the bottom layer components, while maintaining a flat top area for stencilling.

Once I was confident that I could stencil the top area, I started the dry assembly of the top components, starting with the smallest first, so that the big components don’t get in the way of assembly. There were a similar number of small components on the top side, plus the BGAs and QFNs. The dry assembly took about 3 hours on top of the hour of preparations. I then pasted the top side of the CPC2 board, and began the transfer from dry to pasted board. This took about another 45 minutes. I placed 4 scrap boards in the reflow oven at either end of the CPC2 board and gingerly perched the pasted board precariously on top. Any nudge in the wrong place now and it would be all over for this build. I closed the tray and set the oven to a leaded reflow cycle.

As with the paste mask, I should have thought ahead and built a supporting metal jig to go in the reflow oven to hold the board without relying on propping it on scrap boards. Another lesson for next time.

I started to pack up and resigned myself to accept whatever the outcome of this effort. I left the board to cool for 5 minutes before inspecting the result. To my relief, the components on the bottom of the board had not moved at all! Yes, so double sided reflow is possible. Given the complete lack of movement, I suspect that some of the forums advocating leaded solder for double sided boards was also valid. I doubt the bottom side got hot enough to reflow, even for leaded solder and the surface tension would have kept the small passive components on anyway. Note that I hand soldered the bigger components like the JTAG connectors and these were not reflowed.

I also didn’t reflow the USB connection, or the HDMI connection. My nerves got the best of me and I couldn’t see how I could get the relatively large components on the board without unsettling the other placed items. So I left these off for later hand assembly.

First inspection was that the process worked well, except for the USB controller. This was completely mangled. It had burned solder and flux bubbling out from under this device. I clearly had to unmount this chip. I packed up for day 2.

Assembly – Day 3

I started on day 3 with the intention of cleaning up the board and inspecting all the critical joints. I removed the USB chip with a hot air SMT rework station and cleaned the excess solder from the chip pads. It was clear that the paste mask was too ‘open’ and just let a huge mass of solder paste onto the centre ground ‘flag’. This spread out across the pins as I mounted the chip and the sheer volume of paste just led to a runaway cooking of the paste and flux.

When clean up was completed, I further inspected the board and noticed two solder balls bridging pins under the ADV7513 video chip. Dang – this would be hard to fix. A lot of desolder braid and hot iron work pulled the balls out from behind the pins. Unfortunately, I scarred both the board and the chip in the effort, so this isn’t something I’d want to repeat. The ADV7513 also has a large ground flag under the chip and I’m guessing the large mass of solder paste contributed to the balling.

Less is more, so I’ll design future paste masks to deposit paste patterns on the ground flag, rather than leaving it open. A few spots of solder paste would be fine as it spreads out under the chip in reflow conditions.


I had purchased a constant current power supply to facilitate testing and diagnosis of the board. The intention was to slowly power up the device looking for current shorts and rectifying these before applying full power, avoiding burning out parts.

Unfortunately, I realised that there was no way to test the power rails as I had not created any test points to apply the constant current. I couldn’t apply constant current to the +5V supply as the regulators wouldn’t start up and no current would flow beyond these devices. Another point to note here; be sure to create test points for testing the board for first power up. I could have applied +5V at a limited current, but I don’t really have a clear idea of how much power the board will draw. Somewhere in the region of 500-700mA is my guess.

So, I jumped right in, and applied USB power to the USB-B:

No indicator light came on, meaning the 3.3v was shorted somewhere. Grrr!

OK, so now what? I used the very old fashioned method of ‘smoke testing’ to try and work out what was wrong. This means applying the power and seeing what goes up in smoke. Hopefully not the $50 FPGA or $25 HDMI chip. As it turned out the FPGA configuration flash was so hot that it burned the back of my finger. I pulled the power and checked the other chips for heat. The regulators were hot, obviously, but nothing else unusual. The FPGA was hot, but in the normal temperature range. So the configuration flash had to come off. I masked off everything else to apply hot air to the chip:

SMT rework removing the FPGA configuration flash

The aluminum foil would protect the other components from the heat of the air pencil. I applied 320C at half flow rate for about 45 seconds until I was sure the solder was liquid, and then grabbed the chip with tweezers. Within a few seconds it came away. I removed the foil and allowed the board to cool before using the desolder braid and a hot iron to wick away the excess solder on the pads.

I applied power a second time. No, still no power light. At this point, I was at a loss, nothing except the regulators were hot, suggesting a short on the board rather than within a component. An infrared camera would have been helpful here to see which tracks were shorting.

I gambled that the short was under eMMC chip on the basis that it used 0.5mm pitch balls and my application of solder paste was somewhat slapdash under this chip. The pads are too small to use the paste mask. I used 0.4mm paste holes, because anything smaller and the paste doesn’t get through (it’s spec’d to 0.5mm printing). This meant that all the pads were joined by solder paste as the deposited paste spread after printing. I tried the blob-and-scrape method as I have done before, but I was very worried about unsettling the other components on the board, so I didn’t scrape very hard. There must have been bridges between the power lines as I placed this chip. While I was successful with my fake SDCard, I had a lot more time and focus on this single chip to get it working. I had purchased a spare eMMC, so I would remove this chip, to see if I can get the power lines working.

Back on with the aluminum foil and another application of hot air and desolder braid to wick away the excess solder under the eMMC. It was clear that the power lines were shorted here, as there was far too much solder around the bottom rows of the eMMC. After cleaning this up a little, I applied power again.

SUCCESS! We have the LED on!

Removed parts, eMMC and FPGA configuration flash
Note the crazy small pins on the eMMC and the short top right

I checked the heat on the the components again and everything seemed in normal range. So I connected up the JTAG connector for the Atmel SAM4S chip and tested that this was recognised. Yes, this worked. I flashed the firmware and confirmed the USB provided communication to the SAM4 supervisor.

I then moved onto the FPGA JTAG connection, and connected the USB Blaster. Yes, this was recognized with a detect command from Quartus and I selected the correct Cyclone V chip. I tried pushing the bitstream to the FPGA through the JTAG, but it failed.

I tried pushing the bitstream through the ‘Upload’ functionality of the supervisor chip and this worked! Something was wrong with the JTAG connection. Although I could detect the device and an EXTEST or boundary scan would work, a large bitstream like the Quartus FPGA bitstream seemed to fail across this interface. I later read the pin connection guidelines again, and realised that I was missing 1K pull-up resistors on the TMS and TDI lines! I’ll hack these on later, somehow.

I then added on the HDMI connector, and tested the video output. Yes, this worked too! The shadowing and reflections that I’d seen previously were greatly reduced, but not gone completely, so the impedance matching and very short connecting lines had provided a much cleaner signal for the HDMI. I suspect my capture card adds some impedance discontinuities as I see some shadowing on captures from commercial products as well. However, it’s much improved.

I tested a full-white picture, which you may remember caused the monitor to lose lock, and still saw some issues, but didn’t lose the whole picture. There was some flickering and noise that I suspect is related to a non-existent SDC file. I’ll constrain the timing of the output lines and create a virtual clock and hopefully address this issue.

So what next?

So here is what I have now:

  • Working board, which adds an SDRAM chip, but loses the USB chip over the last revision.
  • No FPGA config flash
  • No storage (!)

USB was pretty important, but not dire as I can send scan codes over the supervisor connection.

Config flash is not essential, but would have been a great addition.

The loss of the storage is a problem as without it, this board is completely volatile and state cannot be saved and restored. This means that ROM images cannot be offloaded from the FPGA block SRAM.

I have 4 FPGA lines routed to the ESP-WROOM32 that are currently not used, so I’m intending to re-purpose these to provide BOTH storage and USB connectivity.

Given that the USB connection is purely low-speed USB (1.5Mbps), I believe that two FPGA bi-directional pins can provide USB functionality. I’ll add patch wires between two of the WROOM32 exposed pads and the USB-A connection (currently unpopulated). My experience with the SDRAM bi-directional high speed lines gives me the confidence that I can re-purpose these to be USB pins.

This leaves just 2 lines for a connection to a memory card. The minimum connection for a memory card is 3 lines (MOSI, MISO, CLOCK). That’s a problem.

However, if I add some intelligence between the two lines and the memory card, I can create a serial in/out connection to manage the card data with only two lines providing serial communication. I’ve been investigating using an incredibly full-featured chip from Atmel (I still can’t consider them to be Microchip), the ATtiny841. It has one serial UART and one SPI connection that is perfect for the purpose of this interface. The UART will request a put/get of data and the SPI will push to the card. It’s for this reason that I’ve been investigating how to program these tiny 14-pin devices without a purpose-built programmer.

I’ll also replace the FPGA configuration flash, after working out what I believe went wrong (below).

Lessons Learned

So, here was a big learning exercise. Assuming that the SDRAM interface works, and I can fix the storage and USB connection, I’ll be a little further ahead, but not much. I’ll need another build. Here’s what I take away from this work:

  1. My technique for assembly is slow but reliable. Dry assembly followed by pasting and relocation of components works well.
  2. Double sided assembly works well – yay! A jig would provide some ease of assembly. Also, the bottom layer design should leave some space at the edge of the board for the jig, or a metal crimp can hold the board at the edges and support both assembly and baking.
  3. The paste mask holes are right for the 0.8mm pitch devices like the SAM4S. (No oversized holes, 0.4mm stencil holes). This is the limit of the paste mask. Any smaller will likely cause solder bridges.
  4. The large ground flags under the HDMI chip and USB chips should not be covered with solder paste and paste should be applied sparingly in a regular pattern to avoid wicking and bridges.
  5. DONT use untested parts like the USB3320 on a complex build. If I had tested assembly of this part before using it on this build, I may have been able to correctly mount the USB connection.
  6. While my FPGA configuration flash design would work well after the Atmel SAM4 is programmed, in it’s unprogrammed state, BOTH the SAM4 and the config flash are trying to drive the same lines (DATA0-DATA4), causing the flash chip to overheat. A jumper is needed to pull the nRESET low on the flash while the SAM4 is programmed, so that they don’t both try to drive the same lines.

I’ll test out the SDRAM connection before going any further on this build and report back how that goes. Until next time….

Last Post <====> Next Post


6 thoughts on “Retro CPC Dongle – Part 32

  1. Nice work! The hot parts remind me of the time I found out the hard way that the polarity markers for an electrolytic cap were backwards on the first run of a board. Apply power, make a wish, and blow out the cap-turned-candle 🙂 .

    Liked by 1 person

  2. How’s your CPC project? There was no update for quite some time.. 🙂 Eager to read some news!


    • I spent the first 3 months of this year refining the caching SDRAM controller. It worked fine in simulation, then when I put the design in silicon, I ended up chasing timing issues. I belatedly realised that the expected 800MHz top speed of the device is for the speed grade-6 devices, and I have a speed grade-8 device. According to the specs the logic fabric runs at a maximum of 240MHz, so my 160MHz SDRAM controller was pushing the limits with unoptimised logic. I manged to get it to run at 152MHz with a lot of tweaking and reading about timing closure, but couldn’t optimise the code without a major rewrite. I’ll be doing a full write up on the findings soon. Unfortunately, I got sidetracked into a back up project now that CrashPlan is out of the consumer market. I’ll be back soon and planning more rapid updates. Thanks for checking in.


Leave a Reply

Fill in your details below or click an icon to log in: Logo

You are commenting using your account. Log Out /  Change )

Twitter picture

You are commenting using your Twitter account. Log Out /  Change )

Facebook photo

You are commenting using your Facebook account. Log Out /  Change )

Connecting to %s