Retro CPC Dongle – Part 32

Well, as promised in my last CPC2 post, I finished the next build of the CPC2 board and learned a lot of things during the process. Somethings worked, some things didn’t, but every build is giving me a wealth of knowledge of product design, fault diagnosis and rectification work. Yes, de-solder braid really was my best friend in this build!

Finally, a working board (click here for large)
Bottom side of board (click here for large)

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Arduino ISP

As a brief reprieve from my main CPC2 project, I sidetracked into Arduino programming to solve a problem on the CPC2. I need to create an interface to a memory card, with only two wires. To do this, I’m going to use an Atmel (Microchip) ATtiny841 to interface between the memory card SPI interface and a two-wire serial UART. To program this device without spending heaps of money on a dedicated programmer, I’ll use an Arduino to program the Tiny. This post covers setting up an Arduino to write a bootloader into another Arduino or Atmel chip. To test this process, I used an Freetronics EtherTen to program a Freetronics Eleven that had a damaged bootloader.  I’m using version 1.8.5 of the Arduino IDE.

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Retro CPC Dongle – Part 31

I’ll start with a confession. While I’ve had some success with FPGAs, I managed this despite not understanding some of the basics, such as system design constraints, particularly in Quartus. This post covers both my research into system design/timing constraints and the result of the byte cache that sits on top of the SDRAM controller. I’ll break with my tradition and save the screen grab for the end.

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Retro CPC Dongle – Part 30


“Cache Grab”

Yes, pun intended, this post is about the caching SDRAM controller that I’ve written for the new CPC2.2 board. Here’s the cache (screen) grab:

Cache (Screen) Grab (Click for large)

This screen grab shows one of the key process steps in the caching controller, the cache line replacement. The red bracket indicates the cache i/o ports and some key internal state variables, and the blue bracket indicates the data cache i/o ports on the dual-port ram. Continue reading