Retro CPC Dongle – Part 25.1

Following the last post, I connected the USB packet information to the faked keyboard in the FPGA and managed to get this.

There’s a timing issue that I suspect is interrupt related. The key repeat is extremely slow, and this is mainly driven from the 50Hz interrupt line. I faked this signal, so there’s obviously some work to do there! Stay tuned!

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Retro CPC Dongle – Part 25

What’s wrong with this picture? (Impedance matching and other things)

It’s about time we talked about high speed signals, impedance matching and signal reflections.  Take a look at this picture:

(Very) close up view of the captured CPC screen

There is something clearly wrong with the image above, the pixels are all there and the colours are almost right, but what you’re seeing above isn’t what was sent from the FPGA. What I think I’m seeing here is signal trace length skew and signal reflections.

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