Retro CPC Dongle – Part 17

As I was explaining to someone recently, bootstrapping a completely new, custom design is hard. There are no tools or pre-existing software to manage the device (Atmel/Altera tools aside). Everything has to be built from scratch. It’s been quite a while since I started this project to get to this point, but I’m getting close now to a workable infrastructure. Once the foundation is in place it will allow rapid development of the CPC portions of this project. Here’s the UI part of the work so far:

Supervisor software screen grab (yes, I borrowed the CPC colours for authenticity)

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Retro CPC Dongle – Part 16

It’s been a while since my last post, so I thought it about time I provided an update. I’ve been working on the supervisory software inside the SAM4 microcontroller.

Here are the planned features for this chip:

  • Flash management including flash translation layer
  • MRAM management
  • Provide an interface to the FPGA to access these two memories
  • Provide a debug console for both the monitor program and the FPGA
  • Provide an upload facility to both the FPGA and to memory

To date, I’ve:

  • Written the MRAM interface, using the Atmel ASF libraries to handle the SPI
  • Connected and passed traffic between the FPGA and the SAM4 supervisor using the 40MHz SPI interface
  • Started the user interface for the monitor program. At the moment, all it shows is one active item to upload the bitstream to the FPGA and several templated inactive items.
  • Connected and can read/write the RAW flash layer

Where I’ve gotten bogged down is in the flash translation layer (FTL). Continue reading