OK, so I had a setback. Not a major one, but enough to make me want to go back and redo the design and incorporate all of the learning to date on this project. The key mantra for me is “simplify, simplify, simplify”. If I can do more of the complexity in software rather than hardware without sacrificing the goals of the project, then I’ll do that.
Below is an updated block diagram. Compare this to the original and you’ll see that I’ve simplified the memory interface to connect through an Atmel SAM4S processor. This will handle configuration of the FPGA as well as handling the system storage and pass the data through the support CPU. The system interface (system I/F) will be a fast interface to the internal structures of the FPGA.
The flash memory is required to be connected to the SAM4S because this will also handle the FPGA configuration through the passive parallel port and needs the storage of the flash device to hold the FPGA images. The MRAM is also connected to the SAM4S as this will be used to manage regular configuration changes and assist with the flash translation layer (FTL).
Moving the storage devices off the FPGA will reduce the number of pins required for connection to the FPGA, making the wiring of this device simpler. I’ve added an ESP32 module from Espressif to handle Bluetooth and Wifi. This won’t be available on the first incarnation of the board, but will be added later as the ESP32 becomes available for sale.
So, same functionality, simplified connections, fewer components.
Watch this space.
2 thoughts on “Retro CPC Dongle – Part 9”
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