Retro CPC Dongle – Part 6

This picture says it all, my boards are back from the fab lab!

 

Finished Board (Click for hi-res)

 

Following on from my last postOSH Park came up with the goods again! Within three weeks of submitting the design, the finished boards were in my eager hands. A quick electrical test and brief inspection under a microscope convinces me these are manufactured to spec.

Have a look at the PCB layout from DesignSpark and the equivalent manufactured board image here:

The bright areas are where the copper is exposed so you can see the tracks disappearing under the solder mask as they go dull and back out again. There is a slight registration issue on the solder mask and it’s not quite centered over the pads, but it’s close enough not to affect the quality of the circuit. Here’s an example of where the mask alignment covers part of the pads:

Look at the 5th pad across on the second row up, it looks clipped


And under a brighter illumination you can see the solder mask covering the same pin in the lower right of the pad. These are minor issues as the FPGA is a 1mm pitch and the misalignment is between 0.127mm and 0.254mm. To get an understanding of the scale, the finest traces on this image are 5mil (0.127mm). There’s plenty of clearance between these traces and the pad and the solder mask doesn’t bleed across the clearance.

For my own piece of mind, I checked that the via’s are carrying signals between the layers and checked the track resistance from the 3.3V supply to the furthest contact points on the board. Resistance is R0.1 to R0.2, so no issues there.

I’ve ordered a stainless steel stencil for the solder paste from Osh Stencils, so I expect this to turn up in about 3 weeks. I’ll be placing the order to Mouser for the components soon. These are usually fairly quick, in the order of a week or thereabouts.

Then I’ll need to ask the family nicely if they’ll give me a couple of hours peace to assemble the board. It’s a fairly toxic process with some nasty fumes, so I’ll need some quiet time. Once this is done, I’ll unit test each device soldered to the board. Then the fun of writing RTL for the FPGA begins!

Next up is the solder stencil, in part 7.

 

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