Retro CPC Dongle – Part 5

Exciting news! The CPC2 PCB has gone to the fab lab, OSH Park and is in production as I write this.  I probably should have been reporting progress over the past few months on the schematic and PCB layout, but I’ve opted to use my precious spare time to lay out the PCB so that I know it all fits together before posting. Without further delay, here’s the finished board layout, rendered by the OSH Park service:

And the back side of the board:

With thousands of connections across 4 layers, this is the most complex board I’ve produced to date, so I’m feeling pretty accomplished that I managed to route everything across a 74×51 mm board. It was particularly challenging to route the FPGA as there are a lot of connections in a very small space. The silkscreen could still use some work, but overall I’m pretty happy with the result.

While the board layout looks impressive, the schematics are the key and the PCB layout is the ultimate output for this work.

Let’s take a look at the schematic first. DesignSpark allows you to split your schematic across several sheets and when it translates the schematic to a PCB layout, it combines all sheets into a single board. This allows the schematic to be logically split for readability and allows nets to be shared across sheets.

As I wrote about in previous posts, reading and understanding the data sheet is critical to the success of this project. There are several critical connections to the FPGA, and the FPGA is the central device on the board, I started by wiring this up.

The FPGA connections are categorized as:

  • MSEL – power on configuration scheme, set to active serial
  • Flash Active Serial configuration lines serial in, out, clock and chip select (nCS)
  • FPGA config and status lines, nStatus, nConfig, nCE
  • JTAG connections TCK, TDI, TDO, TMS
  • POWER pins 1.1V , 2.5V, 3.3V, DPLL Power, IO power
  • I/O pins

We start with the MSEL, A/S and JTAG lines on sheet 1. I followed the “Pin Connection Guidelines” from the Altera product page. This walks you through pin-by-pin the recommended connections for power, system and control lines for the FPGA. These are critical to get right because without correctly set-up power, the chip won’t start and with all of the connections hidden underneath the device when it’s mounted, there’s no way to patch the device connections and fix it. Similarly for the configuration, this is critical to the core of the device operation. If I can power up the chip and get the JTAG interface working, then at least I am able to program the device to test the remaining connections.

Top left of the schematic is the Cyclone V configuration pins. I connect in the status pins, the Flash configuration pins and the device configuration (MSEL) pins. For JTAG configuration, MSEL doesn’t matter too much, but I want to be able to configure this from the Flash during normal operation, so MSEL is configured for normal active serial operation. While MSEL is referred to in the documentation, the available settings were not listed, so I had to look up the MSEL settings in the online documentation.

Next, I dropped the FT2232H device on the schematic and wired this up. Again, the data sheet is essential. The datasheet shows how to connect the FT2232H to the JTAG lines on the FPGA. The remaining lines are power, config and IO. I add in a 12MHz clock for the USB connection, and connect the power lines through appropriate filters, being an inductor and two capacitors in parallel (L1, C2, C3 as an example).

Next I connect up the power to abstract power nets. The regulators providing power on these nets are not defined in the schematic yet, but we can still define the links to the FPGA. When we place the regulators and connect the net to their output pins, DesignSpark will automagically link these two components. I connect net V2P5 (2.5V) to AUX, and PLL, 1.1V to VCC and 3.3V to everything else that isn’t GND.

Once this is done, I simply connect every other pin to a bus. In retrospect, the undisciplined manner of assigning pins to device connections probably made the job of routing the lines so much harder. For example, for tightly bound lines like the video connection and memory connections, I would want them all to be on the same side of the device in a tight cluster, in the order that I needed them, near the destination device. As I didn’t do this, I needed a lot of vias on the board to cross these lines over to their respective destination. I’m sure the board could have been a bit smaller if I’d done this and I could avoid any issues with losses, cross talk and routing in these high speed lines.

On sheet 2 of the schematic, I show where these busses are connected on their respective destination devices. Note that the busses are symbolic, they do not translate into any sort of connection, they simply group connections on the schematic. The net name is the mechanism with which these connections are made. The bus names shown on the schematic are for clarity.

For flexibility of design, I’ve simply connected all pins to the FPGA for each device. SDRAM, HDMI video, Flash, MRAM, USB Host. Again the only tricky connections are the power for the HDMI chip, these are likely to require very low noise and stable supplies.

Finally on the last page, I set up the voltage regulators for all of the supply nets in the design, plus the obligatory blinky LED.

Finally, not on the original block diagram, I’ve added an Atmel ATSHA204 crypto chip. It is useful for not just crypto, but also is a hardware random number generator. Could be a useful trade for just one IO pin.

The 0.1uF capacitors scattered on the schematic are just decoupling capacitors that should soak up some of the high frequency noise on the board. I use these at regular intervals on the board to ensure the stability of the devices. These will be routed on the PCB and don’t require configuration in the schematic.

Once I’m happy that I’ve connected the device pins correctly, checking I’ve not crossed input with output connections for example, I can translate the schematics to a board. This is accomplished in the “Translate to PCB” in the DesignSpark menu. It will create a new PCB and place all of the components outside the board outline connected by a ‘rats nest’. Rats nest is a term that just describes unrouted connections from one device pin to another. The task now is to put this huge jigsaw together. I’ll place each chip in approximately the right place based on it’s source and destination, then route the connections to the chip.

The general approach to routing is to pick a direction for the layer you’re working on. Two layer boards have a horizontal size and a vertical side. Four layer boards have a bit more of a choice. I opted for alternating layers of horizontal and vertical. While the traces on the top layer seem to go both horizontally (preferred) and vertically, you’ll notice a preference for horizontal in the middle of the board. Around the edge doesn’t matter so much, so I’ve routed power lines around the edge of most layers. Under the BGA and high density chips there is a relaxing of the rule as you generally are not going to route an unrelated signal under these chips, so you’ll know what’s ‘passing through’. The via’s take board space on all layers simultaneously, so they are used sparingly and you have to route around them even if it means you have to route against the preferred direction to avoid them. My strategy is to use layers sparingly, this means when you really need to route under a mess of tracks, you will probably have a layer to use. Avoid using vias where you can because the vias are much wider than the tracks (18mil via vs 5mil tracks) so they can cause difficult “bulges” and “no-go” areas for tracks on the sub layers as the tracks are routed around the via with sufficient clearance.

To start, I place the FPGA in the center of the board and route the ground pins first, then the V1P1 VCC pins, then the V2P5 pins, finally the V3P3 pins, I make sure I escape these pins from under the BGA footprint in several directions, so that there’s a good quality path to these pins. Once these are done, I place some of the chips with high density connections, such as the HDMI chip and the SDRAM close by the FPGA. I also need the FT2232H close by so I place this also. The HDMI and FT2232H chips have large GND pads under the center of these device so I use these as anchors for the grounding points and route the grounds from the FPGA to these points.

I then route the critical signals for these chips. In the case of the HDMI, the four differential signals are critical as these can run well over 1.5GHz, so it’s important that the traces are uniform length and separation as much as possible. The same goes for the USB connections for the FT2232H and to a lesser extent the 12MHz full-speed USB host.  Once those critical signals are done, I move onto the data lines for HDMI as these run at up to 165MHz for 1080p60. Again, consistency and simplicity are preferred. The next bandwidth hungry connection is the SDRAM at 133MHz, these are routed as simply as possible. Finally onto the FT2232H data lines.

I then move onto the power supplies for the FT2232H and HDMI chip. These use an inductor and capacitor in a structure that I’ve not used before, so it’s a little tricky to know how best to arrange these. The rest of the components are not so difficult as they are low pin count connections, or low speed so the routing is not critical.

Finally I route all the remaining connections. It’s super critical that the PCB is checked for consistency against the schematic and against the design rules. After every few tracks, I run the PCB/Schematic check and the design rules check. These take a second or two, but it’s worth the effort to avoid having to move multiple tracks if something fails the validation. It may sound generous to have 5mil tracks with 5mil clearance, but with some of the BGA pitches at 31mil, this soon gets used up as you can only get one trace between the pads of the BGA. Many of the track routes are run at 5mil tolerance, so the design rules check (DRC) check is a life saver.

The other thing that the DRC checks is whether all of the ratsnest wires have been routed and gives you a count of how many traces are left to route. It’s nice to watch that count down.

Eventually all traces were routed, so I went about reinforcing the main supply and ground nets. Supply lines are routed around the edge of the board and so it’s possible to connect the net to multiple points along the path so that pins at the end of the trace are not starved of current by the pins at the start of the trace. The 3.3V and ground lines were connected at multiple points to ensure a good quality supply and I placed the decoupling capacitors around the board at critical points on the trace. Some of the possibly optional caps were placed on the bottom of the board for hand soldering if needed for stability, mainly because I couldn’t fit anything more on the top side of the board close enough to the requiring device.

I output the traces to gerber and drill files and used GERBV to view the traces in their proper order. Note that I didn’t use any copper fill as this did not render properly, so there must be something unusual about the mechanism that DesignSpark uses. In both the GERBV preview and the OSH Park preview the copper fill bled into other traces, so I opted not to use copper fill. I’ve manufactured a simpler board in the past and experienced the bleeding, so I wasn’t going to risk it with a board this complex.

Once the gerbers were checked for alignment with GERBV, I submitted the package to OSH Park and their excellent site previews the rendered board allowing a visual inspection of the top, bottom and inner layers. A small payment later and the boards are submitted for inclusion in their panelizing process. The lead time on their web site says boards will be despatched within 3 weeks, but within two weeks, I received a notification that the boards are dispatched. Great service OSH Park! I’ve ordered a bunch of boards from them and the quality and performance of their manufacturing is excellent. It doesn’t make sense to use breadboard any more, as most of the useful chips are small pitch and high frequency and this doesn’t work well on breadboard. If you want a quick 2 layer board, these are your guys.

Postage from the united states takes a while, so I’ll be holding my breath waiting for delivery of the boards. As soon as they arrive, I’ll post them up. While I’m waiting, I’ll be ordering a stencil from OSH Stencils.





3 thoughts on “Retro CPC Dongle – Part 5

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