In the last post, I laid out the hardware and architecture planned for this USB-sized 8-bit home-computer. Since then, I’ve been developing the various components in Verilog and testing some of the unknowns. Specifically, I’ve been trying to work out if the memory chip has the required bandwidth for my device.

To do this, I need to study the datasheet for the SDRAM device and understand the best and worst case operating parameters.  One timing diagram for a burst read operation is shown below:

We can see from this that there is a delay between the read operation and the availability of the data.  In the example above, it shows that for every 6 clocks, we get data available during 4 of those T-Cycles.  Combining this information with the expected operating profile is critical to determining if we can service the expected memory requests.

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In my last post I outlined the planned hardware for our CPC dongle.  Now let’s look at how that hardware might fit together.   I’m focussing on the modules internal to the FPGA, as this is where all of the complexity lies.

Behold, the grand design:

This probably needs some explaining! Continue reading →