Month: July 2014

UrJTAG and Python – A lightweight HAL?

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Following up on my last post on a Virtual UART for the DE0 Nano, I’ve been exploring ways to make the logic available on any PC.  The Nano is small and portable enough to carry around and use on any machine, but if you need to install Quartus on it before you can connect through to the logic, it sort of loses it’s portability.

This article is another of my trips ‘down the rabbit hole’.  By that, I mean, when you start something, then find there’s a problem or a dependency and you have to tackle that before you can tackle what you really wanted?  Well, that was this story, but I won’t bore you with the details.  Needless to say, this article describes how to build the very latest version of UrJtag under Linux and generate the very accessible Python interface.

What’s the point of that, you may ask?  Well, UrJTAG is pretty lightweight, multi platform and provides a Hardware Abstraction Layer (HAL) that we can use for a future Python Virtual UART.  You’ll still need to install some files on the target machine, but nothing like the gigabytes of the Quartus installation. Continue reading →

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Virtual UART for the Terasic DE0-Nano

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DE0Nano
Terasic’s DE0-Nano

 

The Terasic DE0-Nano is an excellent device, but it lacks an easily accessible UART to get information in and out of your design.

Fortunately, Altera’s Virtual JTAG functionality allows easy access to logic inside of your design. Chris Zeh wrote an excellent article on this Virtual JTAG functionality and how to easily send data in and out of the chip.  You can read his blog entry here.

This Virtual UART project is an extension of Chris’s work.  It provides a Verilog template to expose a parallel FIFO interface into and out of your design, matched to a TCL script on the PC side.  It allows a simple way to talk to your logic design through a character interface – ideal for a terminal interface to your latest NIOS or OpenRISC SoC.

The example TCL script sets up a network connection on your PC, listening on port 2323. Using Telnet to connect to this port will parse the Virtual JTag instructions to get data in and out of the Virtual UART buffers.

The quickest way to get started is to run the pre-compiled images provided here.  When you’re ready to incorporate this into your own design, all source is available on Github.

Even with no additional hardware, adding a Virtual UART to your design makes the DE0 Nano even more accessible.  If you find this useful, let me know in the comments!