With the world in lockdown, you’d think there’s plenty of time for hobbies. Somehow, it’s been 4 months since my last post – time flies in a crisis! I’ll admit that I’ve been somewhat lax in working on the CPC2, but with the project so close to completion, I need to re-commit to finishing this 5-year project! Today’s post is about my CPC Bluetooth joystick!
So the next build of the CPC2 is done. I recorded the process with a time-lapse camera because it’s hard to make a 7 hour build entertaining. Each second of video is 30 seconds of assembly time, so this 7-hour build ended up at 7m19s of timelapse, after cutting out the cursing and head-scratching. See if you can spot my hands start to shake at the 2-hour mark of trying to precisely place the sub-millimetre components and enjoy.
Doesn’t time fly? It’s been 6 months since my last post! My only excuse is that I started a new job and learning a new culture and processes is pretty exhausting. I have tended to work on this project during the evening, but kids being what they are, rarely co-operate when you need some project time. Time to work on the CPC2 has been limited indeed.
There’s been a fair bit of activity though, so let’s take you though what has been done.
The CPC disk operations are working! The video below shows the CPC loading a disk image from the eMMC, saving new files and unloading the disk image back to the eMMC. The image on the right is the UART console, which is also used to issue the mount and unmount commands (via ‘m’ and ‘u’ commands).
I’ve been struggling for over a week now to get my DE10-Nano board to boot a minimum Linux kernel with no dependencies to the onboard SD Card.
This post is how to get an embedded initial RAM disk or initramfs to boot and provide minimum application services.
Here’s my embedded “INITRD – How-To Guide”
This post talks about HyperRAM, what it is, how to interface to it and how to improve the performance of high-speed parallel interfaces.
HyperRAM is described well by Cypress. It is essentially a double data rate RAM with a compact 12-line interface that masks the underlying technology of a DDR SDRAM. It can provide 333MB/s of data transfer in short bursts. Data is transferred on both edges of the clock, and the narrow bus makes it ideal for microprocessors or pin-constrained FPGAs. Continue reading